IC Verification Engineer

A verification engineer of the highest quality is what Broadcom is looking for. With the capabilities test plans, designing verifiable environments, as well as doing the functional exercise of the trivial blocks and features of the complex SoC, you will be the main responsible figure. Also, working closely with design and architecture, we expect you to bring the highest verification quality and efficiency to the project through this collaboration.

Key Responsibilities

• Accompanying the architectural changes with the creation of test plans for Block, Core, and SoC features, and rendering functional coverage is documented.
• Не def me thod olog ies и сиач In to your work, write and synthesize scalable, reusable test benches.
• To reach the aim of total functional coverage, invent and construct pseudo-random tests.
• Initially, you break down the regression that caused the failure, analyze coverage gaps, and further, you add the tests that will close the gaps.
• Come up with creative ideas on how to push the DUT to its limits and, at the same time, efficiently verify your work.
• Take part in the creation of the documentation for the verification strategy, which includes test plans, environments, and test cases.
• Participate in the stages of design and architecture.
• Be a source of continuous quality and efficiency in verification through your innovation.

Qualifications

• One cannot but speak of a very good B.E. degree in Electrical Engineering (supported with eight years of experience) or a Master’s degree in the same field (supported with six years of experience).
• Working on the problem of writing and debugging a complex testbench, one has to choose one that is a matter of experience.
• A great measure of proficiency in SystemVerilog and methods such as UVM / VMM / OVM.
• Тhe necessary components (attributes and methods) should be used in class in a programming language that describes the object structures, among other OOP principles.
• Working directly with functional coverage, test plans, and pseudo-random tests is a must.
• Familiarity with complex protocols (such as PCIe or other multi-layered communication protocols).
• Capability of self-directed work and production of top-notch outputs.
• Understanding of the PCI Express protocol would be advantageous.